Solar cells are photovoltaic devices that convert sunlight directly into electrical power. The most common solar cell material is silicon, which is in the form of single or polycrystalline wafers. However, the cost of electricity generated using silicon-based solar cells is higher than the cost of electricity generated by the more traditional methods. Therefore, since early 1970's there has been an effort to reduce cost of solar cells for terrestrial use. One way of reducing the cost of solar cells is to develop low-cost thin film growth techniques that can deposit solar-cell-quality absorber materials on large area substrates and to fabricate these devices using high-throughput, low-cost methods.
Group IBIIIAVIA compound semiconductors comprising some of the Group IB (Cu, Ag, Au), Group IIIA (B, Al, Ga, In, Tl) and Group VIA (O, S, Se, Te, Po) materials or elements of the periodic table are excellent absorber materials for thin film solar cell structures. Especially, compounds of Cu, In, Ga, Se and S which are generally referred to as CIGS(S), or Cu(In,Ga)(S,Se)2 or CuIn1−xGax (SySe1−y)k, where 0≦x≦1, 0≦y≦1 and k is approximately 2, have already been employed in solar cell structures that yielded conversion efficiencies approaching 20%. Absorbers containing Group IIIA element Al and/or Group VIA element Te also showed promise. Therefore, in summary, compounds containing: i) Cu from Group IB, ii) at least one of In, Ga, and Al from Group IIIA, and iii) at least one of S, Se, and Te from Group VIA, are of great interest for solar cell applications.
The structure of a conventional Group IBIIIAVIA compound photovoltaic cell such as a Cu(In,Ga,Al)(S,Se,Te)2 thin film solar cell is shown in FIG. 1. The device 10 is fabricated on a substrate 11, such as a sheet of glass, a sheet of metal, an insulating foil or web, or a conductive foil or web. The absorber film 12, which comprises a material in the family of Cu(In,Ga,Al)(S,Se,Te)2, is grown over a conductive layer 13, which is previously deposited on the substrate 11 and which acts as the electrical contact to the device. Various conductive layers comprising Mo, Ta, W, Ti, and stainless steel etc. have been used in the solar cell structure of FIG. 1. If the substrate itself is a properly selected conductive material, it is possible not to use a conductive layer 13, since the substrate 11 may then be used as the ohmic contact to the device. After the absorber film 12 is grown, a transparent layer 14 such as a CdS, ZnO or CdS/ZnO stack is formed on the absorber film. Radiation 15 enters the device through the transparent layer 14. Metallic grids (not shown) may also be deposited over the transparent layer 14 to reduce the effective series resistance of the device. The preferred electrical type of the absorber film 12 is p-type, and the preferred electrical type of the transparent layer 14 is n-type. However, an n-type absorber and a p-type window layer can also be utilized. The preferred device structure of FIG. 1 is called a “substrate-type” structure. A “superstrate-type” structure can also be constructed by depositing a transparent conductive layer on a transparent superstrate such as glass or transparent polymeric foil, and then depositing the Cu(In,Ga,Al)(S,Se,Te)2 absorber film, and finally forming an ohmic contact to the device by a conductive layer. In this superstrate structure light enters the device from the transparent superstrate side. A variety of materials, deposited by a variety of methods, can be used to provide the various layers of the device shown in FIG. 1.
In a thin film solar cell employing a Group IBIIIAVIA compound absorber, the cell efficiency is a strong function of the molar ratio of IB/IIIA. If there are more than one Group IIIA materials in the composition, the relative amounts or molar ratios of these IIIA elements also affect the properties. For a Cu(In,Ga)(S,Se)2 absorber layer, for example, the efficiency of the device is a function of the molar ratio of Cu/(In+Ga). Furthermore, some of the important parameters of the cell, such as its open circuit voltage, short circuit current and fill factor vary with the molar ratio of the IIIA elements, i.e. the Ga/(Ga+In) molar ratio. In general, for good device performance Cu/(In+Ga) molar ratio is kept at around or below 1.0. As the Ga/(Ga+In) molar ratio increases, on the other hand, the optical bandgap of the absorber layer increases and therefore the open circuit voltage of the solar cell increases while the short circuit current typically may decrease. It is important for a thin film deposition process to have the capability of controlling both the molar ratio of IB/IIIA, and the molar ratios of the Group IIIA components in the composition. It should be noted that although the chemical formula is often written as Cu(In,Ga)(S,Se)2, a more accurate formula for the compound is Cu(In,Ga)(S,Se)k, where k is typically close to 2 but may not be exactly 2. For simplicity we will continue to use the value of k as 2. It should be further noted that the notation “Cu(X,Y)” in the chemical formula means all chemical compositions of X and Y from (X=0% and Y=100%) to (X=100% and Y=0%). For example, Cu(In,Ga) means all compositions from CuIn to CuGa. Similarly, Cu(In,Ga)(S,Se)2 means the whole family of compounds with Ga/(Ga+In) molar ratio varying from 0 to 1, and Se/(Se+S) molar ratio varying from 0 to 1.
The first technique that yielded high-quality Cu(In,Ga)Se2 films for solar cell fabrication was co-evaporation of Cu, In, Ga and Se onto a heated substrate in a vacuum chamber. However, low materials utilization, high cost of equipment, difficulties faced in large area deposition and relatively low throughput are some of the challenges faced in commercialization of the co-evaporation approach.
Another technique for growing Cu(In,Ga)(S,Se)2 type compound thin films for solar cell applications is a two-stage process where metallic components of the Cu(In,Ga)(S,Se)2 material are first deposited onto a substrate, and then reacted with S and/or Se in a high temperature annealing process. For example, for CuInSe2 growth, thin layers of Cu and In are first deposited on a substrate and then this stacked precursor layer is reacted with Se at elevated temperature. If the reaction atmosphere also contains sulfur, then a CuIn(S,Se)2 layer can be grown. Addition of Ga in the precursor layer, i.e. use of a Cu/n/Ga stacked film precursor, allows the growth of a Cu(In,Ga)(S,Se)2 absorber.
Sputtering and evaporation techniques have been used in prior art approaches to deposit the layers containing the Group IB and Group IIIA components of the precursor stacks. In the case of CuInSe2 growth, for example, Cu and In layers were sequentially sputter-deposited on a substrate and then the stacked film was heated in the presence of gas containing Se at elevated temperature for times typically longer than about 30 minutes, as described in U.S. Pat. No. 4,798,660. More recently U.S. Pat. No. 6,048,442 disclosed a method comprising sputter-depositing a stacked precursor film comprising a Cu—Ga alloy layer and an In layer to form a Cu—Ga/In stack on a metallic back electrode layer and then reacting this precursor stack film with one of Se and S to form the absorber layer. U.S. Pat. No. 6,092,669 described sputtering-based equipment for producing such absorber layers. Such techniques may yield good quality absorber layers and efficient solar cells, however, they suffer from the high cost of capital equipment, and relatively slow rate of production.
One prior art method described in U.S. Pat. No. 4,581,108 utilizes a low cost electrodeposition approach for metallic precursor preparation. In this method a Cu layer is first electrodeposited on a substrate. This is then followed by electrodeposition of an In layer and heating of the deposited Cu/In stack in a reactive atmosphere containing Se. Although low-cost in nature, this technique was found to yield CuInSe2 films with poor adhesion to the Mo contact layer. In a publication (“Low Cost Thin Film Chalcopyrite Solar Cells”, Proceedings of 18th IEEE Photovoltaic Specialists Conf., 1985, p. 1429) electrodeposition and selenization of Cu/In and Cu/In/Ga layers were demonstrated for CIS and CIGS growth. One problem area was identified as peeling of the compound films during solar cell processing. Later, in another reference (“Low Cost Methods for the Production of Semiconductor Films for CIS/CdS Solar Cells”, Solar Cells, vol. 21, p. 65, 1987) researchers studied the cross-section of Mo/CuInSe2 interface obtained by the above-mentioned method and found the CuInSe2 to have poor adhesion to the Mo contact layer.
Irrespective of the specific approach used in a two-stage process, growing for example a Cu(In,Ga)(S,Se)2 absorber film, individual thicknesses of the layers forming the metallic stacked structure need to be controlled so that the two molar ratios mentioned before, i.e. the Cu/(In+Ga) ratio and the Ga/(Ga+In) ratio, can be kept under control from run to run and on large area substrates. The molar ratios attained in the metallic stacked structures are generally preserved in macro scale during the reaction step, provided that the reaction temperature is kept below about 600° C. Therefore, the overall or average molar ratios in the compound film obtained after the reaction step is about the same as the average molar ratios in the metallic stacked structures before the reaction step. In prior art approaches all the Cu, In and/or Ga required for the final desired molar ratios are deposited on the substrate before the reaction step with S and/or Se. In other words, to grow a Cu0.8In0.8Ga0.2Sex, where x is close to 2, for example, the prior art techniques typically deposit a Cu/In/Ga stack, a In/Cu/Ga stack or a Cu—Ga/In stack, so that the Cu/(In+Ga) molar ratio of the stack is 0.8 and the Ga/(Ga+In) molar ratio of the stack is 0.2. This metallic stack is then selenized at high temperatures to form the compound. One problem associated with such approaches is that these precursors are relatively thick (500-1500 nm) and are typically rich in Group IIIB components of In and Ga, which have low melting points of about 156° C. and 30° C., respectively, and they cause micro-scale non-uniformities, as will be discussed next.
FIGS. 2a-2c demonstrate the problem of micro-scale non-uniformities which may be present in the metallic precursor layers, especially those with IB/IIIA molar ratios of less than or equal to 1. FIG. 2a schematically shows an exemplary Cu/In/Ga metallic stack with the exemplary overall molar ratios of Cu/(In+Ga)=0.8 and Ga/(Ga+In)=0.2 on a substrate. In this approach, a contact film 21 is first deposited onto a substrate 20, forming a base 22. A Cu layer 23 is then deposited over the contact film 21. The thickness of the Cu layer 23 may, for example, be about 200 nm. This Cu thickness and the desired molar ratios cited above require deposition of about 440 nm thick ID layer and about 80 nm thick Ga layer. These calculations can be made assuming densities of Cu, In and Ga to be 8.96 g/cc, 7.31 g/cc and 5.91 g/cc, respectively, and the atomic weights to be 63.54 g, 114.76 g and 69.72 g, respectively. Using a density value of 5.75 g/cc and a molar weight of 306.66 g for the selenized compound of Cu0.8In0.8Ga0.2Se1.9, it is also calculated that the metallic precursor of this example would yield approximately 1880 nm thick CIGS layer, assuming 100% density. The optimum thickness of CIGS layers for thin film solar cell applications is in the range of 500-5000 nm, preferably in the range of 700-2000 nm, smaller thicknesses being preferable because it reduces materials cost.
Referring back to FIG. 2a, deposition of about 200 nm thick Cu layer 23 is followed by the deposition of a nominally 440 nm thick In layer 24 and a nominally 80 nm thick Ga layer 25. The Cu layer 23 in the resulting metallic precursor stack 26 is shown as smooth and uniform, whereas, the In and Ga layer surfaces are depicted as non-planar. Although the surface morphologies of these layers depend strongly on the deposition techniques used, it is generally true that low-melting-temperature metals such as In and Ga tend to “ball” when deposited in thin film form, especially if they are deposited on top of each other. It should be noted that melting temperature of (Ga+In) mix is lower than the melting temperature of In which is around 156° C.
The metallic precursor layer 26 of FIG. 2a may have the desired Cu/(In+Ga) and Ga/(Ga+In) molar ratios in a global sense or in macro scale. However, in micro scale the situation is quite different as can be seen in FIG. 2b which shows a magnified view of the region 27 of FIG. 2a. Since the In layer thickness “t1” at and around point “A” is much larger than the In layer thickness “t2” at point B, the local Cu/(In+Ga) ratio is much smaller at and around point “A” than at and around point “B”. Furthermore Ga/(Ga+In) ratio is also different at these two points, i.e. higher at point B compared to point A. It should be appreciated that after the reaction step with Se these micro-scale non-uniformities in the molar ratios of the metallic components are mostly transferred to the compound, yielding a CIGS layer that has in-plane compositional variations due to varying Cu/(In+Ga) and Ga/(Ga+In) ratios. This situation is schematically shown in FIG. 2c, which depicts a compound layer 29 obtained by reacting the precursor stack of FIG. 2b with Se. The region R1 in FIG. 2c corresponds approximately to the area around point A in FIG. 2b and the region R2 corresponds approximately to the area around point B in FIG. 2b. Accordingly, region R1 is an In-rich region and region R2 is a Cu-rich region. It should be noted that boundaries between these regions may not be as defined as suggested in FIG. 2c. Boundaries are shown as such just to demonstrate the point. In real films even the crystalline structures of these regions may be different. Cu-rich regions, after selenization, may contain large faceted grains of Cu-selenides, whereas, In or Ga-rich regions would be smoother with smaller grains. When a solar cell is fabricated on the compound layer 29 of FIG. 2c, the copper rich region R2 containing highly conductive Cu-selenide phases would increase the leakage current across the device and reduce its voltage output, whereas the In-rich region R1 would increase its series resistance. Both effects would deteriorate the solar cell efficiency if they are extreme. Since the non-uniform surface morphologies such as the one depicted in FIGS. 2a-2c vary from run to run and from substrate to substrate, repeatability of the manufacturing process of this solar cell would also be poor and the yield for high efficiency large area device fabrication would be low. For best solar cell efficiencies and high manufacturing yields compound layers with macro-scale as well as micro-scale compositional uniformity are needed.
It should be noted that the example given above explained the micro-scale non-uniformity problem for the case of non-uniform or rough Group IIIA layer deposited on a smooth Group IB layer. However, similar problems are observed even if the morphologies of In and Ga layers were smooth in their as-deposited state. The reason is that even if the starting morphologies of In and Ga were smooth, during the reaction step with the Group VIA material, such as Se, the metallic precursor is heated up, typically to temperatures above 350° C. As the heating step is performed, In and Ga start to melt at temperatures above about 30° C. before reacting with the Group VIA material and they de-wet the substrate they are deposited on such as the Cu surface. This de-wetting phenomenon forms “balls” giving rise to rough morphologies similar to the one shown in FIG. 2b. Furthermore, balling becomes more extensive as the amount of the low-melting phase (in and/or Ga) in the stack is increased or the thickness of In and/or Ga layers are increased.
FIG. 3a shows an exemplary metallic precursor stack 36 deposited over a base 22, wherein the base 22 comprises a substrate 20 and a contact film 21 as in FIG. 2a, and the metallic precursor stack 36 comprises a substantially smooth Cu layer 33, a substantially smooth In layer 34 and a substantially smooth Ga layer 35, which may be deposited onto the base 22 by various thin film deposition techniques such as evaporation, sputtering or electrodeposition by taking certain measures such as keeping the base at below room temperature by forced cooling during deposition. In this example, the individual Cu, In and Ga layers within the stack 36 have flat surface morphologies. FIG. 3b shows the morphology of this precursor stack after it is heated up to a temperature of for example 160° C., which is higher than the In melting temperature as well as the melting temperature of the (Ga+In) composition lying over the Cu layer 33. Since the (Ga+In) composition of our example is 20% Ga and 80% In, the melting temperature is in the range of 100-120° C. according to the In—Ga binary phase diagram. The surface morphology of the (In+Ga) layer of FIG. 3b is very non-uniform and would give rise to the micro-scale compositional non-uniformities in the compound layers fabricated using such precursors as described before with reference to FIGS. 2a, 2b and 2c. It should be noted that although the interface between the Cu layer 33 and the (In+Ga) layer 36a of FIG. 3b is shown to be sharp, this interface in practice may be diffused depending upon the temperature of the heat treatment step.
One approach to address the micro-scale non-uniformity problem is described in U.S. Pat. No. 5,567,469 awarded to Wada et al. In this approach a portion of the low-melting phase or component, e.g. indium, is introduced into the precursor layer in the form of a compound selected from the group consisting of oxides, selenides and sulfides. These compounds of In have very high melting points. Therefore, when the precursor is heated up to perform the reaction step with Group VIA component(s), melting and balling of In is reduced since at least some of the In is in the form of a high melting point compound.
The discussion above concentrated on the problem of micro-scale compositional non-uniformities in metallic precursor layers used in prior art two-stage process approaches. An additional important problem, namely adhesion, was also identified for metallic precursor layers obtained by the low cost electrodeposition technique. Although electrodeposition is attractive to use in terms of its lower cost, there are other limiting factors in using the prior art electroplating approaches for the preparation of metallic Group IB and Group IIIA elemental stacks for the fabrication of Group IBIIIAVIA compound films as will be described below.
Cu, In and Ga have very different plating potentials. The molar standard electrode potentials of Cu/Cu2+, In/In3+ and Ga/Ga3+ metal/ion couples in aqueous solutions are about +0.337 V, −0.342 V, and −0.52 V, respectively. This means that Cu can be plated out at low negative voltages. For In deposition, on the other hand, larger negative voltages are needed. For Ga deposition even larger negative voltages are required. Therefore, to form a stack containing Cu, In and Ga, Cu is typically electroplated first. This is then followed by deposition of In and then Ga. Otherwise, while electroplating one species, the other species on which deposition is carried out may partially dissolve into the electrolyte. For example, if a stack of Cu/Ga/In is electrodeposited, while depositing In over Ga, some Ga may be dissolving into the In deposition solution. This then would lead to poor control over Cu/(Ga+In) and Ga/(Ga+In) molar ratios in the precursor and the absorber layer after its formation. Similarly, deposition of a Cu layer over an In layer may result in loss of In from the In layer into the Cu plating electrolyte during processing. Therefore, prior-art methods have employed Cu/In/Ga stacks electroplated in that order. However, after selenization such stacks yielded compound layers with poor adhesion to the base or the substrate. Furthermore, compositional micro-scale non-uniformities such as those described with reference to FIGS. 3a and 3b did not allow formation of high quality Group IBIIIAVIA layers suitable for the fabrication of high efficiency solar cells. It should be appreciated that thin film deposition techniques with adhesion problems cannot be reliably scaled up for manufacturing of electronic devices, especially solar cells which are expected to have a lifetime of over 20 years.
As the brief review above demonstrates, there is still a need to develop low-cost deposition techniques to form high-quality, dense, well-adhering Group IBIIIAVIA compound thin films with macro-scale as well as micro-scale compositional uniformities.